1. Field of the Invention
This invention relates generally to the field of digital storage systems employing non-volatile memory devices such as flash memory and particularly to decreasing the time associated with writing information to the nonvolatile memory devices thereby increasing overall system performance.
2. Description of the Prior Art
Recently, solid state memory has gained popularity for use in replacing mass storage units in various technology areas such as computers, digital cameras, modems and the like. For example, in digital cameras, the use of solid state memory, such as flash memory, replaces conventional films.
Flash memory is generally provided in the form of semiconductor devices (or chips) with each device made of a large number of transistor memory cells and each cell being individually programmable. The programming (or writing) and erasing of such a memory cell is limited to a finite number of erase-write cycles, which basically determines the lifetime of the device. Furthermore, an inherent characteristic of flash memory cells is that they must be erased and verified for successful erase prior to being programmed.
Accordingly, use of flash memory entails erasing the area of memory that once contained information every time prior to re-programming the same area. In a flash memory device, write and erase cycles are generally time-consuming thereby significantly reducing the performance of a system utilizing flash memory as its mass storage.
In applications employing flash memory devices, such as personal computers and digital cameras, a host writes and reads information to the flash memory devices through a controller device, which is commonly in the form of a semiconductor device. Such information is organized in sectors with each sector including user data information and overhead information, collectively referred to as sector information. The user data portion of a sector is typically 512 bytes in length although other size sectors may be similarly employed. The controller, upon receiving sector information from the host, during a host-commanded write operation, writes sector information to the flash memory devices in accordance with a predetermined sector organization. While the host may be accessing multiple sectors, each sector is written to the flash devices one at a time.
In storing and/or retrieving a data file (data files may be any computer files including commercial software, user program, word processor software document, spread sheet file and the like), a computer (or host) system provides what is referred to as the logical block address indicating the location of where the host believes the data file to exist within the mass storage. The host-provided address may be in the form of cylinder, head and sector (CHS), which is converted to a logical block address format upon receipt by the controller. The same applies to digital camera applications. The controller then translates the logical block address (LBA) into a virtual logical block address (VLBA) and uses the latter to look-up a virtual physical block address (VPBA) within a space manager look-up-table (LUT). Upon retrieving the VPBA, the controller uses the same to access the data file within flash memory. The data file is stored in blocks within the nonvolatile memory with each block having a predetermined number of sectors. For example, a block comprises 16 sectors and each sector includes 512 bytes of user data information and various bytes of extension or overhead information, such as flags, ECC and the like. The VPBA is translated into a PBA for locating a particular block within the nonvolatile memory.
Each time a data file is changed, the latest version of the file is stored in an available (or `unused`) location within the flash memory that is identified by a new physical location (or new PBA). Upon using much of the free (or available) locations within the flash memory for updated files, an erase operation may be needed to make available `old` locations for storage of additional information. Since erase operations are time-consuming (as are write operations), there is a tradeoff as to the frequency of performing erase operations to the time expended for searching for free locations within the flash memory as more and more locations are used prior to the next erase operation. Efforts are continuously made to try and find ways of improving system performance by reducing the number of erase operations or reducing the search time associated with locating blocks of information within the nonvolatile memory.
Information in the nonvolatile memory or flash memory is stored under the direction of the controller and it is done so in the form of sectors and a number of sectors define a block. A block may include 16, 32 or other number of sectors. But once blocks are determined to include a predetermined number of sectors, this determined size defines each block. Thus, information that is stored in nonvolatile memory is organized in blocks and each block is uniquely addressable by the controller. Each block is further comprised of multiple sectors with each sector being defined by 512 bytes plus additional storage space for storing non-data information, such as flags, address and error correction code (ECC) information. Although a sector may have data storage spaces other than 512 bytes. In some prior art systems, during an erase operation, an entire block is erased whereas in other prior art systems, the sector may be erased. Each sector within a block is uniquely addressable for reading and writing information from and to the nonvolatile memory. A unique value is maintained within each block that contains sector information as a Virtual Logical Block Address (VLBA) for use in reconstructing the addressing or mapping information associated with the nonvolatile memory during power-up. As is well known by those skilled in the art, when power is lost, information maintained in volatile memory, such as Random Access Memory (RAM) is lost. The mapping information regarding the block information stored within the nonvolatile memory is generally maintained in a look-up-table (LUT) within volatile memory, as will now be further described.
Currently, in computers wherein large files such as commercial software and user programs are stored within flash memory and in digital cameras wherein large picture files are stored within flash devices, the files are written one sector at a time within flash. Due to the latency associated with each write operation, the performance of these systems when storing large quantities of information is limited. Some of the steps associated with a write operation performed on a particular sector is to shift a write command into the flash (memory) device being written, shift sector information into the flash device being written and then start to write (or program) the write command followed by the sector information into the block within which the sector information is to be stored. Generally, for a 512-byte sector, 30 .mu.sec. is needed to shift sector information into the flash device. 200 .mu.sec. is needed to actually write the sector information into the flash device. One of the limitations of prior art systems is that one sector is written at-a-time, thus, more than 230 .mu.sec. are needed to write each sector. Where each block contains 16 sectors that must be written thereto, more than 16.times.230 .mu.sec. is necessary to write all of the sectors, which considerably slows system performance when writing many sectors.
One way prior art systems have attempted to overcome this problem is by addressing two sectors at-a-time to allow for writing of two sectors at-a-time. While these prior art techniques decrease the actual sector information write time by a factor of two, there is still twice as much time needed to shift two sectors worth of sector information. In the example provided hereinabove, 200 .mu.sec. (as opposed to 400 .mu.sec.) is required to perform the actual writing of 1024 bytes of sector information, however, 2.times.30 .mu.sec. or 60 .mu.sec. is required to shift 1024 bytes of sector information. Thus, to write two sectors having 512 bytes of user data, a total of approximately 260 .mu.sec is required. To help in understanding such prior art systems, an example is provided by reference to FIGS. 1 and 1a.
In FIG. 1, a prior art digital storage system 600 is shown to include a flash device 602 and a flash device 604. Each flash device is organized into blocks of information starting from Block 0 and continuing in sequential order to Block N (N being an integer number). Two blocks in like locations within the flash devices are used to write 32 sectors of information as each block of a flash device, in this example, includes 16 sectors. The sectors are numbered with even sectors being stored in flash device 602 and odd sectors being stored in flash device 604 although this is an arbitrary design choice and the opposite may be done. The sectors are numbered so as include 32 sectors within a two-block location distributed over two flash devices. Moreover, the numbering of the sectors causes switching between the flash devices in that, for example, the first sector, S0, appears in the first sector storage location of the first block, Block 0, of the flash device 602, the second sector, S1, appears in the first sector storage location of the first block, Block 0, of the flash device 604, the third sector, S2, appears in the second storage location of the first block, Block 0, of the flash device 602, the fourth sector, S3, appears in the second storage location of the first block, Block 0, of the flash device 604.
The reason for the even and odd numbering of the sectors between the two blocks of each of the flash devices is to enable loading of sector information in-parallel using a data bus, DB7:0 616, for coupling sector information to and from the flash deice 602 and another data bus, DB15:7 624 for coupling sector information to and from the flash device 604. A FCE0* signal 620 enables or selects the flash devices for shifting command/address and sector data and overhead information therein when active. The signal 620, in this example, is an active low signal.
FIG. 1a is a timing diagram of the signals depicted in the prior art FIG. 1 for use in explaining the operation of the latter. In FIG. 1a, the data bus DB15:0 is effectively a combination of the busses 616 and 624 and the WE* signal is one of the signals included in the control signals 622. When low, the WE* signal causes shifting of information into the flash devices. Initially, command and address information for sectors S0 and S1 is shifted into the flash devices. Next, sector user data and ECC information is shifted into the flash devices. Flash device 602 receives 512 bytes of data through the 616 bus and flash device 604 recevies 512 bytes of data through the 624 bus. Upon completion of shifting of all of the sector information, the controller starts the write operation, which causes the Frdy/Bsy* signal 618 to be activated (goes from a high state to a low state). Serial shifting of the command/address information and shifting of the sector information and the start of the write command consume approximately 30 .mu.sec. in the case where each sector includes 512 bytes of user data. When the Frdy/Bsy* signal 618 goes low, approximately 200 .mu.sec. thereafter, the writing (or programming) of sector information (user data and ECC) is completed for a sector having 512 bytes. Actually, in this case, in 200 .mu.sec., 512 words (each word being two bytes) is programmed because the two busses 616 and 624 couple information to the flash devices 602 and 604, respectively and in-parallel. Thus, the entire write operation takes approximately 230 .mu.sec. to complete. Upon completion of writing to sectors S0 and S1, the same process takes place for programming sectors S2 and S3 followed by programming of S4 and S5.
Some of the limitations with the prior art technique that was just discussed and described in FIGS. 1 and 1a are that there are more physical input/output pins required on the controller device. Specifically, due to having two data busses, 616 and 624, there are twice as many data bus lines necessary. In fact, if this prior art technique was to be used for programming more sectors in parallel and thus having additional flash devices configured in-parallel, the requirement for added data busses would increase and ultimately the number of controller pins would be impractical. Just as an example, to have four flash devices in-parallel where four sectors may be programmed in parallel, there would be an additional 16-number of pins needed on the controller device (for 16 additional data bus signals totaling 32 signals). This clearly increases manufacturing costs related to the controller device and may lead to a larger device that additionally drives costs higher.
Another drawback related the prior art system of FIGS. 1 and 1a is that prior to the beginning of the shifting of the first sector information, the host need load the buffer with the number of sectors that are to be programmed otherwise, the time to program the sectors increases substantially. This affectively leads to a bigger buffer size, which increases manufacturing costs.
Thus, while such prior art techniques cut the time required for performing sector write operations by processing two sectors at-a-time, additional time, i.e. double the time for shifting sector information, is nevertheless necessary to complete the write operation.
Therefore, the need arises for a method and apparatus to decrease the amount of time associated with a controller device's writing of sector information to nonvolatile memory by performing some of the tasks associated with writing to one sector in-parallel with writing to another sector thereby increasing overall system performance while maintaining the pin-count of the controller device the same and avoiding additional costs in connection with manufacturing of the system.